Program - Workshops


7-3 - Robotics Workshop

Tuesday, August 28, 2018
4:45 pm – 6:15 pm


Have fun as you learn about robotics with this introductory course! From understanding sensors to programming robots for missions, this course will quip you with hands-on experience in building and programing robots and help you set up after-school STEM-Robotics clubs for your local community children. The hands-on lessons are taught by award winning teams from Education Empowers, Inc. (501 (c) non-profit) as well as industry professionals.


Oliver Chen

Anna Prakash received her Ph.D from Arizona State University in Chemistry under the guidance of Prof. Dr. Karl Booksh. She began her engineering career at Three-Five Systems Inc., an electronic display manufacturer, working on Liquid Crystal Displays, HDTVs and hand held communication devices. She joined Intel Corporation, in 2004 as a Packaging Research & Development Engineer and is currently a Senior Materials Engineer. In addition to being a key contributor for over 20+ technical publications, Anna is also a prolific inventor with over 20+ patents (granted/filed) covering sensors, displays, optoelectronics, and semiconductor packaging materials & process. Outside of work, Anna is passionate about promoting STEM, robotics and sustainability education for local children. Along with her daughter Elaina, she co-founded Education Empowers Inc., a non-profit promoting STEM education for children. She mentors junior engineers, girls, underserved and underrepresented children in STEM through her non-profit Education Empowers Inc. ( Anna is the recipient of the Society of Women Engineers "Prism Award" and the IEEE STEM outreach award for her contribution to technology and the community.

7-4 - Maker and AI Workshop

Wednesday, August 29, 2018
4:45 pm – 6:15 pm


Learn how to combine the Raspberry PI and the Intel Movidius Neural Compute Stick to bring the power of AI to the edge.



Oliver Chen

Oliver Chen is a Technical Marketing Engineer supporting AI in the Sales and Marketing Group at Intel Corporation. He is passionate about the intersection of leading-edge technology and new business opportunities. He thrives in expanding the STEAM pipeline by making AI and Maker content easier to consume.

Priyanka Dobriyal

Priyanka Dobriyal is a Product Engineer in Datacenter group at Intel Corporation. She is a Ph. D in Chemistry from University of Massachusetts, Amherst and MS from Indian Institute of Technology, Roorkee, India. She is passionate about leading STEM outreach related activities.

Alex (Shih-To) Fei

Alex (Shih-To) Fei is a Project Manager and Engineer perfecting cutting-edge 14nm and 10nm technology at Intel LTD. He also functions as Community Lead and Project Manager at Intel Makers Oregon, organizing events in collaboration with IOTG and Outreach Programs. Alex joined Intel after receiving PhD degree at Penn State in 2010.

7-5 - Heat Sink Additive Manufacturing Workshop

Wednesday, August 29, 2018
4:45 pm – 6:15 pm


The ASME K-16 Committee is proud to sponsor a student design competition focused on the development of novel heat sinks built with Additive Manufacturing (AM) techniques. GE Additive is the Platinum Sponsor for this initiative and will provide valuable metal printing time for the fabrication of the unique, intricate, and effective heat sinks developed by top undergraduate students from Universities around the world. AM is a disruptive and pervasive technology, and these students will bring a fresh and energetic perspective to the design of low-cost and efficient heat sinks. The top four student groups will present and justify their heat sink design approach to technical leaders at InterPACK. Join us at the San Francisco Financial District Hilton from August 27-30 for an opportunity to see tomorrow's leaders in our field vie for the title of K-16's top student design team!

Heterogeneous Integration Roadmap (HIR) Panel

Thursday, August 30, 2018
3:15 PM – 6:15 PM
Room: Mason I, Second Floor

Welcome to the Heterogeneous Integration Roadmap Panel hosted by the 2018 ASME InterPack Conference!

Our Industry has reinvented itself through multiple disruptive changes in technologies, products and markets. With the rapid migration of logic, memory and applications to the Cloud infrastructures, Data Centers and 5G Networks, the Internet of Things (IoT) to internet of everything (IOE), Autonomous Vehicles, the proliferation of Smart Devices everywhere, and increasing interest in artificial intelligence (AI) & Virtual Reality (VR), the pace of innovation is increasing to meet these challenges. What are the paths forward?

The IEEE Heterogeneous Integration Technology Roadmap (HIR), is sponsored by the IEEE Electronic Packaging Society (EPS), the Electron Devices Society (EDS), Photonics Society together with ASME EPPD and SEMI. It will address the future directions of heterogeneous integration technologies and applications serving future markets and applications, so very crucial to our profession, our industries, academic and research communities. Following the spirit of ITRS, the HIR is a pre-competitive technology roadmap provides long-term vision to identify the needs of future technology challenges, roadblocks, and potential solutions focused on system integration and broad market applications in order to accelerate progress for the broad electronics industry.


  • Introduction - Bill Chen & Bill Bottoms
  • Heterogeneous Integration Roadmap Overview - Ravi Mahajan
  • Invited Speaker - TBD
  • Heterogeneous Integration TWG Panel Session
    Panel Moderator - TBD
    • High Performance Computing & Data Center - Rockwell Hsu
    • 2.5D & 3D - TBD
    • Thermal Management - Madhu Iyenger
    • Reliability - Abhijit Dasgupta
    • 5G & Analog & Mixed Signal - Tim Lee
    • Emerging Devices - Meyya Meyyapan
  • Wrap-Up - Bill Bottoms & Bill Chen

Ravi Mahajan

Ravi Mahajan, Intel Corporation, Santa Clara, CA

Ravi Mahajan is an Intel Fellow and the Co-director of Pathfinding and Assembly and Packaging technologies for 7nm silicon and beyond in the Technology and Manufacturing Group at Intel Corporation. He has led efforts to define and set strategic direction for package architecture, technologies and assembly processes at Intel since 2000, spanning 90nm, 65nm, 45nm, 32nm, 22nm and 7nm silicon. Ravi holds more than 40 patents (including the original patent for a silicon bridge that became the foundation for Intel’s Embedded Multi-Die Interconnect Bridge technology) and has written several book chapters and more than 30 papers on topics related to his area of expertise. He has been nominated as an IEEE CPMT Distinguished Lecturer. He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT. Additionally he has been long associated with ASME’s InterPACK conference and was Conference Co-Chair of the 2017 Conference. Ravi is a Fellow of two leading societies, ASME and IEEE.

Abhijit Dasgupta

Dr. Abhijit Dasgupta, University of Maryland, College Park, MD

Abhijit Dasgupta is Jeong H. Kim Professor of Mechanical Engineering at the University of Maryland (UMD), with research experience in the microscale and nanoscale mechanics and reliability physics of engineered materials used in conventional and additively manufactured 3D flexible electronic packaging and intelligent microsystems. He holds a Ph.D. in Theoretical and Applied Mechanics from the University of Illinois at Urbana-Champaign (UIUC), and has been a principal investigator at the Center for Advanced Life Cycle Engineering (CALCE) at UMD for the past 30 years, conducting research in reliability physics, design for reliability, accelerated stress testing, and real-time health management. He is an ASME Fellow, past Chair of the ASME Electronic and Photonic Packaging Division (EPPD), current member of the ASME Design, Manufacturing and Materials Segment Leadership Team (DMM-SLT) and Reliability Topic Lead in one of the Technical Working Groups (TWGs) of the Heterogeneous Integration Roadmap (HIR) Team.

Rockwell Hsu

Dr. Rockwell Hsu is a Technical Leader at Cisco Systems, Inc. where he leads an initiative on advanced semiconductor packaging development for 112Gbps and beyond for network equipment and SI/PI development for network line cards used in switches and routers. Prior to Cisco, he led RF and server CPU packaging development at Intel. Dr. Hsu holds one US patent. Dr. Hsu was the chair of the High-Speed, Wireless & Components Committee for the IEEE Electronic Component Technology Conference (ECTC) and has been a member of the ECTC since 2006. Dr. Hsu was the chair of Santa Clara Valley Chapter of the IEEE Antennas and Propagation Society (APS).

William Bottoms

William Bottoms, Patricof & Co. Ventures, Radnor, PA

Dr. Bottoms received a B.S. degree in Physics from Huntington College in Montgomery, Alabama in 1965, and a Ph.D. in Solid State from Tulane University in New Orleans in 1969 and is currently Chairman of Third Millennium Test Solutions. He has worked as a faculty member in the department of electrical engineering at Princeton University, manager of Research and Development at Varian Associates, founding President of the Semiconductor Equipment Group of Varian Associates and general Partner of Patricof & Co. Ventures. Dr. Bottoms has served as Chairman and CEO of many companies both public and private.

Mark Shaw

Mark Shaw, Microsoft, Redmon, WA

Mark Shaw is Director of Hardware Engineering for Microsoft’s Cloud and AI Division, responsible for the architecture and hardware designs of Compute & Storage platforms utilized in Azure’s cloud scale services. Mark is leading the Project Olympus open source hardware development effort with the Open Compute Project to bring leading edge technology to the community. Microsoft’s Open Compute Project servers have been deployed at massive scale across a global fleet of data centers. Mark’s team is responsible for delivering leading-edge technology as the HGX-1 GPU AI accelerator and SmartNIC FPGA accelerator. Mark holds over 30 patents in computing systems and hardware. Prior to Microsoft, Mark was a Distinguished Technologist at Hewlett-Packard and cut his teeth designing systems, platform controllers, CPUs and coherent interconnects at Gould and Convex Supercomputers.

Meyya Meyyappan

Meyya Meyyappan, NASA Ames Research Center, Washington, DC

Meyya Meyyappan is a fellow of IEEE, ASME, MRS, ECS, AVS, IOP, AIChE and National Academy of Inventors. He has received numerous awards including a Presidential Meritorious Award and Induction into Silicon Valley Engineering Council Hall of Fame.